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- 1 - SM8521 contents description .............................................................. 2 features .................................................................... 2 pin connections ..................................................... 3 block diagram ....................................................... 4 pin description ....................................................... 5 absolute maximum ratings ............................. 6 recommended operating conditions ............. 6 dc characteristics ............................................. 7 sm85cpu ...................................................................... 8 register lineup address space rom area register file area ram area data format bus timing system control .................................................. 18 oscillator circuit clock system memory map hardware reset interrupt function standby function i/o ports ................................................................... 29 timer/counters .................................................... 30 clock timer watchdog timer register (wdt) lcdc/dma .................................................................. 33 vram configuration dma transfer compound and overwrite mode registers sound generator ............................................... 41 sound waveform register registers mmu ............................................................................. 45 universal asynchronous receiver and transmitter (uart) interface ......................... 47 uart transmit data register (urtt) uart receive data register (urtr) uart status register (urts) uart control register (urtc) transfer format instruction set .................................................... 51 definition of symbols instruction summary addressing mode system configuration example .................. 55 SM8521
description the SM8521 is a cmos 8-bit single-chip micro- computer containing sm85cpu core and the required peripheral functions for dot matrix lcd display system. sm85cpu is an 8-bit high performance cpu with various addressing modes and high-efficiency instruction sets. sm85cpu is featured by allocating general registers on ram to reduce overhead when calling subroutines. the peripheral functions and memory of SM8521 contain rom, ram, mmu, lcd controller, dma, sound generator, timer, serial interface (uart) and pio. features ?rom capacity : 4 096 x 8 bits ?ram capacity : 1 024 x 8 bits ?external memory expansion ?a ram area is used as subroutine stack ?cpu core : 8 bits x 8 ports (or 16 bits x 4 ports) and 16 bits x 4 ports general purpose register are used as accumulator, register pointer, and register index. instruction sets 67 (multiplication/division/bit manipulation instruc- tion) addressing mode 23 types system clock cycle 0.2 s (min.) at 10 mhz main clock cycle ?system clock is variable by software (system clock can be optioned to 1/2, 1/4, 1/8, 1/16, 1/32 of main-clock and 1/2 of sub-clock.) ?built-in main clock oscillator for system clock ?built-in sub clock oscillator for real time clock ?interrupts : non-maskable interrupts x 2 maskable interrupts x 8 ?standby modes : halt mode/stop mode ?i/o ports : input / output 32 ?timer : 8 bits x 2 (with 8 bits prescaller) clock timer x 1 (1 s or 1 min) watchdog timer ?mmu : in each 8 k-byte unit, external memory can be expanded up to max. 2 m bytes. ?lcd controller : display size 160 x 100 dots 160 x 160 dots 160 x 200 dots 200 x 100 dots 200 x 160 dots black & white 4 gradations (interframe elimination) vram 160 x 200 dot x 2 phases or 200 x 160 dot x 2 phases (required externally) ?dma : transmission mode : rom to vram, vram to vram, extend ram to vram, vram to extend ram transmission data : rectangle (arbitrary size) ?sound generator : arbitrary waveform x 2 (16-level tone, 32- step/1-period waveform output) noise x 1 channel ?pio : i/o 8-bit x 4 (in each 2 bits, i/o, pull-up and open-drain can be set.) ir carrier generator built-in. ?uart : 1 channel baud rate : timer 0 output only (timer 0 output/32) SM8521 SM8521 8-bit single-chip microcomputer (controller for hand-held equipment) - 2 - in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device.
?serial interface : uart 8-bit clock asynchronous x 1 ?clock output ?supply voltage : 4.5 to 5.5 v ?packages : 128-pin qfp (qfp128-p-1420) SM8521 - 3 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nc d7 d6 d5 d4 d3 d2 d1 d0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 31 rdb 32 wrb 33 mce0b 34 mce1b 35 ioe0b 36 ioe1b 37 gnd 38 gnd 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vd1 nc nc vd2 vd3 vd4 vd5 vd6 vd7 vce0b vce1b vrdb vwrb p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 72 p1 6 p1 7 71 p1 5 70 p1 4 69 p1 3 68 p1 2 67 p1 1 66 nc 65 nc 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 gnd osc1 osc2 nc intb nmib resetb m0 m1 m2 v dd r x db t x db p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 p0 6 59 p0 7 60 x1 61 x2 62 gnd 63 clk 64 p1 0 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 gnd vr sound doffb fr lp xc xd0 xd1 xd2 xd3 yd va12 va11 va10 va9 va8 va7 va6 va5 108 va4 107 va3 106 va2 105 va1 104 va0 103 vd0 pin connections 128-pin qfp top view
SM8521 - 4 - block diagram rdb wrb va0-va12 vd0-vd7 intb nmib sm85cpu ram 1 k-byte uart p0 lcdc/dma ram 4 k-byte mmu bus controller timer 8-bit : 2 ch clock watchdog timer sound generator osc vrdb, vwrb vce0b, vce1b xd0-xd3 fr, lp, xc yd, doffb x2 x1 clk a0-a20 d0-d7 mce0b, mce1b ioe0b, ioe1b osc2 osc1 vr sound r x db t x db p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 p0 6 p0 7 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p3 6 p3 7 d/a p1 p2 p3 gnd v dd resetb m0-2
- 5 - SM8521 pin name i/o function d0-d7 i/o external data bus a0-a20 o external address bus mce0b o chip enable 0 (mask rom/flash memory) mce1b o chip enable 1 (sram) ioe0b o i/o enable 0 (address : ff00-ffff) ioe1b o i/o enable 1 (address : ff00-ffff) rdb o read strobe wrb o write strobe nmib i non-maskable interrupt intb i external interrupt vd0-7 i/o vram data bus va0-12 o vram address bus vce0b o vram chip enable 0 (a000-bfff) vce1b o vram chip enable 1(c000-dfff) vrdb o vram read strobe vwrb o vram write strobe p0 0 -p0 7 i/o i/o port 0 p1 0 -p1 7 i/o i/o port 1 p2 0 -p2 7 i/o i/o port 2 p3 0 -p3 7 i/o i/o port 3 rxdb i uart data input port txdb o uart data output port sound o sound output vr i d/a converter reference voltage fr o lcd drive waveform lp o display data latch pulse xc o display data clock xd0-xd3 o diaplay data yd o vertical timing doffb o display off x1 i main clock input x2 o main clock output clk o system clock output osc1 i subclock input osc2 o subclock output resetb i reset m0-m2 i operation mode (usually gnd) v cc , gnd i power supply pin description
SM8521 - 6 - absolute maximum ratings parameter symbol condition rating unit supply voltage v dd 0.3 to 6.5 v input voltage v i 0.3 to v dd + 0.5 v output voltage v o 0.3 to v dd + 0.5 v output current i oh high-level output current 4 ma i ol low-level output current 4 ma operating temperature t opr ?0 to +60 ?c store temperature t stg ?0 to +140 ?c recommended operating conditions parameter symbol condition rating unit supply voltage v dd 4.5 to 5.5 v system clock frequency f sys v dd = 4.5 to 5.5 v 16.384 k to 5 m hz maximum main clock frequency f ck v dd = 4.5 to 5.5 v 10 mhz subclock frequency f sub v dd = 2.7 to 5.5 v 32.768 khz operating temperature t opr ?0 to +60 ?c note : be sure to resetb when power on because internal signal reguires initialization. normal operation is not guaranteed without hardware reset.
- 7 - SM8521 notes : 1. applicable pins : p0 0 -p0 7, p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , d0- d7, vd0-vd7, x1, m0-m2 2. applicable pins : resetb, osc1, rxdb, nmib, intb 3. applicable pins : p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , vd0-vd7, x1, m0-m2 (non-connected pull-up resistor) 4. applicable pins : resetb, p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 (connected pull-resistor) 5. applicable pins : p0 0 -p0 7, p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , d0- d7, a0-a20, mce0b, mce1b, ioe0b, ioe1b, rdb, wrb, va0-va12, vce0b, vce1b, vwrb, txdb, xc, lp, fr, clk, xd0-xd3 6. no load condition, v dd = 5 v, main clock = 10 mhz 7. no load condition, v dd = 5 v, sub clock in active (32.768 khz), vr = gnd, input signal fixation. 8. no load condition, v dd = 5 v, sub clock in active (32.768 khz), vr = gnd, input signal fixation. including lcd, dma, sound generator and any part concerned with timer operation. 9. no load condition, v dd = 5 v, sub clock in active (32.768 khz), vr = gnd, input signal fixation. 10. no load condition, v dd = 5 v, osc1 = gnd, vr = gnd, input signal fixation. dc characteristics parameter symbol unit note input voltage v ih1 0.8 x v dd v dd v 1 v ih2 v dd ?0.5 0.5 10 v 2 v il2 i ih1 ? ? 3 4 i il1 ?0 i il2 ?0 ?5 ?50 0.5 8 10 0.10 45 18 70 6 0.05 30 15 30 1 output voltage v oh1 v dd ?0.5 v bits k v ma 7 8 9 10 ? ? 5 6 v ol1 d/a supply current i dd i ddh i dds1 i dds2 min. v in = v dd , v dd = 5 v v ih = 0 v, v dd = 5 v v in = 0 v, v dd = 5 v i oh1 = ? ma, v dd = 5 v i ol1 = 10 ma, v dd = 5 v vr = v dd = 5 v vr = v dd = 5 v vr = v dd = 5 v f sys = 5 mhz f sys = 5 mhz, halt mode f sub oscillation, stop mode f sub stop, stop mode max. typ. v il1 0 0.2 x v dd input current resolution combined tolerance output resistance (v dd = 4.5 to 5.5 v, t opr = ?0 to +60?c) condition
- 8 - SM8521 sm85cpu the sm85cpu is an 8-bit cpu with an unique architecture, developed by sharp, and the following features. general purpose register architectures there are eight 8-bit general purpose registers (also serve as four 16-bit general purpose registers) and four 16-bit general purpose registers serve as accumulator, index register, or the pointer registers. general purpose register allocated at ram the general purpose registers access the ram location by the register pointer rp. so pushing the register during an interrupt and passing parameter to subroutine can be executed in high speed. refined instruction set the instruction set contains total 67 members : 8 load instructions, 19 arithmetic instructions, 7 logic instructions, 9 program control (branch) instruction, 8 bit manipulation instructions, 8 rotate & shift instructions and 9 cpu control instructions. there are powerful bit manipulation instructions includes plural bits transfer, logical operation between bits, and the bit test and jump instructions that incorporates a test and condition branch in the same instruction. (refer to table 1) ?there are data transfer, arithmetic and conditional branch instructions for 16-bit. it can rapidly process the word-sized and long jump. there are 8-bit x 8-bit ? 16-bit multiplication and 16-bit x 16-bit ? 16-bit remaining 8-bit division instructions. (unsigned arithmetic) 23 address modes the rich address modes provides optimal access to rom, ram and the register files. illegal instruction detecting function when an error code is detected, a non-maskable interrupt (nmi) will be generated. standby function there are two standby modes, halt and stop mode, and the mode can be changed by halt instruction or stop instruction respectively. table 1 instruction summary type instruction number load instruction clr, mov, movm, movw, pop, popw, push, pushw 8 arithmetic instruction adc, adcw, add, addw, cmp, cmpw, da, dec, decw, div, exts, inc, incw, mult, neg, sbc, sbcw, sub, subw 19 logic instruction and, andw, com, or, orw, xor, xorw 7 program control instruction bbc, bbs, br, call, cals, dbnz, iret, jmp, ret 9 bit manipulation instruction band, bclr, bcmp, bmov, bor, btst, bset, bxor 8 rotate & shift instruction rl, rlc, rr, rrc, sll, sra, srl, swap 8 cpu control instruction comc, clrc, di, ei, halt, nop, setc, stop 8 total 67
SM8521 - 9 - table 2 addressing mode summary name symbol range operand * 1 implied to specify the carry(c) and interrupt enable (i) in the instruction code. register r r = r0-r7 general register [byte] register pair rr r = rr0, rr2, ?, rr14 general register [word] register file r r = 0 to 255 (r0-r15) register file (0000 h -007f h ) and (0080h-00ff h ) [byte] register file pair rr r = 0, 2, ?254 (rr0, rr2, ?, rr14) register file (0000 h -007f h ) and (0080h-00ff h ) [byte] register indirect @r r = r0-r7 memory (0000 h -00ff h ) [byte] register indirect auto increment (r)+ r = r0-r7 memory (0000 h -00ff h ) [byte] register indirect auto decrement ?r) r = r0-r7 memory (0000 h -00ff h ) [byte] register index n(r) * 2 n = 00 h -ff h , r = r1-r7 memory (0000 h -00ff h ) [byte] register pair indirect @rr rr = rr0, rr2, ?, rr14 memory (0000 h -ffff h ) [word/byte] register pair indirect auto increment (rr)+ rr = rr0, rr2, ?, rr14 memory (0000 h -ffff h ) [word/byte] register pair indirect auto decrement ?rr) rr = rr0, rr2, ?, rr14 memory (0000 h -ffff h ) [word/byte] register pair index nn(rr) * 3 nn = 0000 h -ffff h rr = rr2, rr4, ?, rr14 memory (0000 h -ffff h ) [word/byte] index indirect @nn(r) * 2 nn = 0000 h -ffff h r = r1-r7 memory (0000 h -ffff h ) [word] immediate im im = 00 h -ff h the immediate data in the instruction code [byte] immediate long iml iml = 0000 h -ffff h the immediate data in the instruction code [word] bit b b = 0 to 7 register file (0000 h -007f h ) and memory (0080 h -00ff h , ff00 h -ffff h ) [bit] (1 bit of 1 byte pointed by r, n(r) and dap) port p register file (0010 h -0017 h ) [byte] relative ra pc ?128 to pc + 127 program memory (1000 h -ffff h ) direct da da = 0000 h -ffff h memory (0000 h -ffff h ) [byte] direct short das das = 1000 h -1fff h program memory (1000 h -1fff h ) direct special page dap dap = ff00 h -ffff h program memory (ff00 h -ffff h ) [byte] direct indirect @da da = 0000 h -ffff h memory (0000 h -ffff h ) * 1 the data indicated by [ ] is the unit of possible to use in load and arithmetic instructions. * 2 r0 can not be used. * 3 rr0 can not be used.
SM8521 - 10 - register lineup fig. 1 shows the sm85cpu register lineup. the cpu internal register consists of eight 8-bit general purpose registers (r0-r7), four 16-bit general purpose registers (rr8-rr14), a program counter (pc) and four other control registers. (the r0-r7 can be also used as four 16-bit general purpose registers (rr8-rr14).) general purpose register the eight 8-bit general purpose registers r0-r7 and all eight 16-bit general purpose registers (rr0- rr14) are available for use as accumulator, index register and pointer registers. (the r0 and rr0 cannot be used as index register) the other eight 8-bit registers r8-r15 cannot be used as 8-bit general purpose register and as member of the register file. (about register file, refer to "address space.") the feature of the sm85cpu architecture is that general purpose registers are virtually allocated at 16-byte internal ram. actually, if the cpu accesses general purpose registers , the designated ram will be accessed by the 5-bit register pointer (rp) ] . when rp = 00000b, the registers occupy the first 16 bytes starting at 0000 h . incrementing the field, rp = 00001b, shifts the mapping by eight bytes so that the registers start at 0008 h . as a result, the general purpose registers can be switched in 8-byte unit to any ram location within 0000 h -00ff h . although the general purpose registers are members of the register file, which stores the data onto actual ram, is different from the other members (control registers). that is, general purpose registers can be referred as registers, as register file (allocated at 0000 h -000f h ) and as ram accessing by all addressing modes. * about register pointer (rp), refer to "processor status 0 (ps0)". rr0 rr2 rr4 rr6 r8 r10 r12 r14 rr8 rr10 rr12 rr14 r0 r2 r4 r6 7 15 07 0 r1 r3 r5 r7 r9 r11 r13 r15 0 70 70 70 70 70 0 15 ps0 ps1 sys spl sph pc fig. 1 register lineup
SM8521 - 11 - cpu control register the sm85cpu has the following control register : processor status ps0, processor status ps1, system configuration register sys, stack pointer sph, spl and program counter pc. all control register except the program counter pc are members of the register file and accessible by the register file r and the register file pair rr addressing modes. processor status 0 (ps0) the processor status ps0 is an 8-bit readable/ writable register containing 2 fields, the upper 5-bit is register pointer (rp) and the lower 3-bit is interrupt mask. bit 7 0 bits 7 to 3 : register pointer (rp) this gives, in 8 bytes unit, the starting address in ram for general purpose registers . bits 2 to 0 : interrupt mask bits (im) internal ram address r0 r1 r14 r15 high low rp im ps0 ex.) if rp = 00000b, general purpose registers will be virtually allocated at internal ram 0000 h -000f h . if rp = 00001b, general purpose registers will be virtually allocated at internal ram 0008 h -0017 h . fig. 2 register pointer (rp) setting example bit content 000 all maskable interrupts recognized 001 010 maskable interrupts with level 1 to 12 recognized 011 maskable interrupts with level 1 to 10 recognized 100 maskable interrupts with level 1 to 8 recognized 101 maskable interrupts with level 1 to 6 recognized 111 maskable interrupts with level 1 tto 4 recognized 111 maskable interrupts with level 1 to 2 recognized pr4 pr3 pr2 pr1 pr0 im2 im1 im0
- 12 - SM8521 processor status 1 (ps1) the processor status ps1 is an 8-bit readable/ writable register and consists of eight flag bits. these flags can be used as the condition codes for the conditional branch instructions. when cpu generates an interrupt, the content of processor status ps1 and the value of program counter pc automatically are pushed onto stack. bit 7 0 bit 7 : carry (c) it indicates that generated a carry in operation. bit 6 : zero (z) it indicates that the operation result is zero. bit 5 : sign (s) it indicates that the operation result is negative (sign bit = ??. bit 4 : overflow (v) executes the operation with the signed value. if the operation result cannot indicate complement on two, then the bit will be ?? bit 3 : decimal adjustment (d) it indicates that the last arithmetic operation is a subtraction. bit 2 : half carry (h) it indicates that generated a carry between bit 3 and 4. bit 1 : bit (b) it indicates that the result of the last bit manipulation. bit 0 : interrupt enable (i) this is a flag which enables /disables all maskable interrupt. system configuration register (sys) the system configuration register sys is an 8-bit readable/writable register which sets the external memory expansion modes and selects 8-bit/16-bit stack pointer. bit 7 0 bit 7 : sets '0' bit 6 : stack pointer configuration (spc) bits 5 to 3 : set '0' bits 2 to 0 : memory configuration (mcnf2-0) * : in rom space (60 k bytes), the field beyond the internal rom is the external memory access field. stack pointer (spl, sph) the stack pointer spl, sph are 8-bit readable/ writable register and show the stack address. the bit spc of the system configuration (sys) specifies whether the stack pointer is 8 (spl only) or 16 (both spl and sph) bits long. program counter (pc) the program counter (pc) is a pointer for program memory and contains the starting address for the next instruction. the program counter pc is initialized to 1020 h after hardware reset. that is, the application program starts executing from the address 1020 h after hardware reset. 0 bit 8-bit (spl only) content 1 16-bit (both spl, sph) - spc - - - mcnf2 mcnf1 mcnf0 czsvdhb i bit content 000 external memory expansion disable. 110 external memory expansion mode (64 k bytes ] ) other combination do not use. bit 15 0
SM8521 - 13 - 76543210 msb lsb msb upper 8-bit lsb lower 8-bit address high low data format 0000 h -00ff h 0000 h -00ff h even byte, 0000 h -00fe h , following byte (odd byte) 0000 h -00ff h register file address bit byte word bcd data type 70 upper bcd digit lower bcd digit 0000 h -00ff h or ff00 h -ffff h 0000 h -00ff h 0000 h -00ff h or ff00 h -ffff h (under shorthand) 0000 h -fffe h following byte 0000 h -00ff h memory address fig. 3 register file/memory data formats address space the sm85cpu has a 64 k-byte address space, which is divided into ram (0000 h -0fff h ) and rom (1000 h -ffff h ) areas. the address 0000 h -007f h are both shared by ram and register file. fig. 9-1 shows the SM8521 memory map. the ram and register file allocated at 0000 h -007f h can be selected by the addressing mode designated by instructions. the SM8521 supports an memory management unit used to external memory area expantion. refer to "memory management unit (mmu)". rom area rom area starts at the address 1000 h of the space address. the first portion (1000 h -101f h ) is reserved for the interrupt vector table. each 2 bytes entry in the vector table contains the address of interrupts. when an interrupt encountered, the cpu jumps to the corresponding branch address of vector table for program executing. the address 1020 h marks the start of the user program area itself. executing always starts at 1020 h after hardware reset. register file area the register file is allocated between 0000 h and 007f h . the first 16 bytes (0000 h -000f h ) area are general registers. the remainder is for cpu control registers, peripherals control register and data register. ram area the ram area starts at the beginning 0000 h of the address space. it overlaps the register file for the address 0000 h -007f h . this arrangement is to shorten the instruction length as much as possible and to permit the use with both ram and the register file for faster execution.
- 14 - SM8521 data format the sm85cpu supports four data types : bit, 4-bit bcd, byte, and word data. register file data formats the register file (0000 h -007f h ) and ram (0080 h - 00ff h ) accessible with register file r and register file pair rr addressing support processing for all 4 data types : bit, 4-bit bcd, byte, and word data. fig. 3 shows the data layout in the register file. bit data (register file) bit manipulation instructions access bit data in the register by register file r addressing, which gives the byte address in the register file (0000 h -007f h ), or ram (0080 h -00ff h ), and the operand b, which gives the bit number within the byte. byte data (register file) instructions access the byte data in the register file by register file r addressing, which gives the byte data address in the register file (0000 h -007f h ) or ram (0080 h -00ff h ). word data (register file) instructions access word data in the register file by register file pair rr addressing, which gives the word address, even and 2 bytes address, in the register file (0000 h -007f h ) or ram (0080 h -00ff h ). the address must be even (0, 2, 4,? 254). specifying an odd address leads to unreliable results. bcd data (register file) the decimal adjust instruction (da), used to adjust bcd digits after an odd or subtraction, accesses a bcd data byte in the register file by register file r addressing. notice for the general register on register file the general registers are the first 16 bytes (0000 h - 000f h ) in the register file. they can be accessed as byte-sized by register file r addressing and as word-sized by register file pair rr addressing. memory data formats the memory area (rom and ram 0000 h -ffff h ) supports processing for all 4 data types : bit, 4-bit bcd, byte and word data. however, bit data is limited to the ranges (0000 h -00ff h , ff00 h -ffff h ), and 4-bit bcd data to the ranges 0000 h -00ff h . fig. 3 shows the data layout in memory. bit data (memory) bit manipulation instructions access bit data in memory by register index n(r) addressing, which gives the byte address in the range (0000 h -00ff h ), or by direct special page dap addressing, which gives the byte address in the range (ff00 h -ffff h ), and the operand b, which gives the bit number within the byte. byte data (memory) instructions access the byte data in memory by shorthand (0000 h -00ff h or ff00 h -ffff h ) or full (0000 h -ffff h ) address. word data (memory) instructions access the word data, continue 2 bytes, in memory by shorthand (0000 h -00ff h or ff00 h -ffff h ) or full (0000 h -ffff h ) address. unlike word data in the register file, the address can be even or odd. bcd data (memory) the decimal adjust instruction (da), used to adjust bcd digits after an odd or subtraction, accesses a bcd data byte in memory by register index @r addressing. notice for general register on memory the general registers are actually in a ram area specified by register pointer rp, so they can be read and modify directly as ram. while programming, the programmer must take care to arrange program data so that other ram operations do not destroy general registers content.
SM8521 - 15 - bus timing the sm85cpu is variable for system clock. the bit fcpus2-fcpus0 (bits 5 to 3 : ckkc) of the clock changing register ckkc can select system clock to 1/2, 1/4, 1/8, 1/16 and 1/32 of the main clock and 1/2 of sub-clock. the cpu operates at 1/32 clock of the main clock after hardware reset. internal memory access timing the read cycle of internal ram is 2 cycles. the internal ram supports 2 cycles for reading or writing. external memory access timing the external memory supports 2 cycles for reading or writing. fig. 5 shows the read timing and fig. 6 shows the write timing. instruction prefetch the sm85cpu, which execution cycle overlaps with the op code, fetches next instruction op code during one instruction execution cycle. for example, the execution time for 2 bytes instructions (mov r, r) of transferring the ram contents to a register is 4 cycles. internal clock pre-instruction transfer instruction next instruction fetch cycle execution cycle executing preinstruction op code fetch operand fetch ram read register write op code fetch execution time fig. 4 instruction execution for transfer instruction (2 bytes)
SM8521 - 16 - rdb valid data d 0 -d 7 t rhd t rha t rsa t rsd t wrd a 0 -a 20 ?external memory access timing (read timing) operating condition (v dd = 4.5 to 5.5 v, t opr = ?0 to 60?c) parameter symbol unit note address setup time t rsa t sys t sys + 50 ns 1 read data setup time t rsd t sys /2 ?30 ns 1 rdb signal pulse width t wrd t sys ?50 t sys ns 1 address hold time t rha 0 ns read data hold time t rhd 0 ns min. typ. max. note : 1. t sys : the system clock period (main clock x 1/2) when the low order 3 bits in the clock change register fcpus2-fcpus0 are 100 b . t rsa : the time between address firm and rdb signal falling low level firm. t rsd : the time between rdb signal firm and input valid data firm. t wrd : rdb signal low level width. t rha : the time between rdb signal rising high level firm and address change. t rhd : the time between rdb signal rising high level firm and output data floating. load capacitance is 50 pf. fig. 5 external memory access timing (read timing)
SM8521 - 17 - wrb d 0 -d 7 valid data t wsa invalid data t wsd t whd t wha t wwr a 0 -a 20 ?external memory access timing (write timing) operating condition (v dd = 4.5 to 5.5 v, t opr = ?0 to 60?c) parameter symbol unit note address setup time t wsa t sys t sys + 50 ns 1 data setup time t wsd t sys ?50 t sys + 30 ns 1 wrb signal pulse width t wwr t sys ?60 t sys ns 1 address hold time t wha 10 ns data hold time t whd 10 ns min. typ. max. note : 1. t sys : the system clock period (main clock x 1/2) when the low order 3 bits in the clock change register fcpus2-fcpus0 are 100 b . t wsa : the time between address firm and wrb signal falling low level firm. t wsd : the time between wrb signal rising high level firm and output valid data firm. t wwr : wrb signal low level width. t wha : the time between wrb signal rising high level firm and address change. t whd : the time between wrb signal rising high level firm and output data floating. load capacitance is 50 pf. fig. 6 external memory access timing (write timing)
SM8521 - 18 - system control oscillator circuit the SM8521 is built-in the main-clock and sub- clock oscillator circuits for generating clock signal. the main-clock oscillator circuit is applied to 1.5 to 10 mhz. the sub-clock oscillator circuit is applied to 32.768 khz. clock system the SM8521 uses the main-clock and sub-clock oscillator circuits to generate the required clock. the system clock, leads cpu operation, is one of the five clocks which divides the main-clock (f ck ) into 1/2, 1/4, 1/8, 1/16 and 1/32. it also selects from sub-clock (f 32k ). in addition, the clocks supplied to the peripheral functions are fc 1 -fc 10 divided by the prescaler prs0 and derived from the 1/2 clock of main-clock (f ck /2), and fx 1 -fx 8 divided by the prescaler prs1 and derived from the sub- clock. f ck = 11.0592 mhz system clock frequency control cg sm85cpu warming up counter sub-clock generator circuit prescaler prs1 ck in ck out osc in osc out ram register read/write function blocks operation peripheral functions interrupt control f ck /2 f c 1 -f c 10 f c 10 system clock f 32k f 32k f 32k = 32.768 kh z main-clock generator circuit 1/2 prescaler prs0 f ck fig. 7 SM8521 clock system
SM8521 - 19 - clock change register (ckkc) clock change register ckkc is an 8-bit readable/ writable register containing the control of system clock change and the setting of warming up period after waking up from the stop mode. clock change register ckkc is initialized to 00 h after hardware reset. bit 7 0 bit 7 : clock change enable bit (fcpuen) bit 6 : main-clock stopped bit (mckstp) main-clock stopped allows switching to sub-clock used as system clock. bits 5 to 3 : system clock selection bits (fcpus2-fcpus0) under the bit fcpuen = ?? if executes the stop instruction, the bits will be valid. bit 2 : reserved bit (tfcpu) always write ??to this position. writing a ? produces unrealiable operation. bits 1 to 0 : warming up selection bits (wups1-wups10) the bits are able to set the warming up period of after wake up from stop mode. bit system clock frequency 000 system clock = (1/32) x main-clock 001 system clock = (1/16) x main-clock 010 system clock = (1/8) x main-clock 011 system clock = (1/4) x main-clock 101, 110 reserved 100 system clock = (1/2) x main-clock 111 system clock = (1/2) x sub-clock bit warming up period after stop mode releases (when main-clock (f ck ) = 10 mhz) 00 2 18 x main-clock period (26.21 ms) 01 2 17 x main-clock period (13.10 ms) 10 2 16 x main-clock period (6.553 ms) 11 2 15 x main-clock period (3.276 ms) fcpuen mckstp fcpus2 fcpus1 fcpus0 tfcpu wups1 wups0 fig. 8 SM8521 clock system (equivalent circuit for clock system peripheral blocks) f ck main-clock 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 cg system clock f sys 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 5 selector f 32k f 32k f ck /4 f ck /8 f ck /16 f ck /32 system clock frequency control prescaler prs0 (frequency divider on f ck /2) prescaler prs1 (frequency divider on f 32k ) sub-clock f c 10 f c 11 f c 12 f c 13 f c 14 f c 15 f c 16 f x 1 f x 2 f x 3 f x 4 f x 5 f x 6 f x 7 f x 8 8 f ck /2 f ck /2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 f c 12 f c 13 f c 14 f c 15 prescaler prs2 (frequency divider on fc 10 ) warming up counter (frequency divider on fc 10 ) for warming up counter 8 to function blocks bit content 0 disables system clock speed change 1 enables system clock speed change bit content 0 main-clock operation 1 main-clock stop
SM8521 - 20 - memory map fig.9 shows the SM8521 memory map. ram physically present area rom physically present area register file physically present area reserved area external rom external rom external rom external rom external rom internal rom reserved area interrupt vector area * 3 vram extend i/o extend ram * 1 * 2 0000 h 0080 h 007f h 0400 h 03ff h 1000 h 0fff h 1020 h 101f h 2000 h 1fff h 4000 h 3fff h 6000 h 5fff h 8000 h 7fff h a000 h 9fff h e000 h dfff h ffff h * 1 rom disable (in case of mmu0 is set.) * 2 rom enable (at reset) * 3 write only during cpu access 0000 h general register general register general register control register system configuration register clock change register stack pointer reserved stack pointer processor status 0 processor status 1 e control register r0 r1 r15 sys ckc sph spl ps0 ps1 0001 h 000f h 0010 h 0018 h 0019 h 001a h 001b h 001c h 001d h 001e h 001f h 0020 h 007f h address space register file interrupt vector dma (dma) (upper) (lower) 1000 h 1001 h timer 0 (tim 0) (upper) (lower) 1002 h 1003 h reserved (upper) (lower) 1004 h 1005 h external interrupt (extint) (upper) (lower) 1006 h 1007 h uart transmit/receive completion (uart) (upper) (lower) 1008 h 1009 h reserved reserved (upper) (lower) 100a h 100b h (upper) (lower) 100c h 100d h lcd controler (lcdc) (upper) (lower) 100e h 100f h reserved (upper) (lower) 1010 h 1011 h timer 1 (tim 1) (upper) (lower) 1012 h 1013 h reserved (upper) (lower) 1014 h 1015 h clock (ck) (upper) (lower) 1016 h 1017 h reserved (upper) (lower) 1018 h 1019 h input/output port (pio) (upper) (lower) 101a h 101b h watchdog timer (wdtint) (upper) (lower) (upper) (lower) 101c h 101d h nmi, illegal instrtuction (nmi, ill) 101e h 101f h fig. 9-1 SM8521 memory map (1)
SM8521 - 21 - fig. 9-2 SM8521 memory map (2) address register name r/w initial value 0000 h general purpose register r0 rr0 r/w undefined 0001 h general purpose register r1 r/w undefined 0002 h general purpose register r2 rr2 r/w undefined 0003 h general purpose register r3 r/w undefined 0004 h general purpose register r4 rr4 r/w undefined 0005 h general purpose register r5 r/w undefined 0006 h general purpose register r6 rr6 r/w undefined 0007 h general purpose register r7 r/w undefined 0008 h general purpose register r8 rr8 r/w undefined 0009 h general purpose register r9 r/w undefined 000a h general purpose register r10 rr10 r/w undefined 000b h general purpose register r11 r/w undefined 000c h general purpose register r12 rr12 r/w undefined 000d h general purpose register r13 r/w undefined 000e h general purpose register r14 rr14 r/w undefined 000f h general purpose register r15 r/w undefined 0010 h interrupt enable register 0 ie0 r/w 00 h 0011 h interrupt enable register 1 ie1 r/w 00 h 0012 h interrupt request register 0 ir0 r/w 00 h 0013 h interrupt request register 1 ir1 r/w 00 h 0014 h pio data register 0 p0 r/w 00 h 0015 h pio data register 1 p1 r/w 00 h 0016 h pio data register 2 p2 r/w 00 h 0017 h pio data register 3 p3 r/w 00 h 0018 h reserved - - 0019 h system configuration register sys r/w * 0000000 001a h clock change register ckc r/w 00 h 001b h reserved - - 001c h stack pointer h sph sp r/w undefined 001d h stack pointer l spl r/w undefined 001e h processor status register 0 ps0 r/w undefined 001f h processor status register 1 ps1 r/w ******* 0 address register name r/w initial value 0020 h pio control register 0 p0c r/w 00 h 0021 h pio control register 1 p1c r/w 00 h 0022 h pio control register 2 p2c r/w 00 h 0023 h pio control register 3 p3c r/w 00 h 0024 h mmu data register 0 mmu0 r/w 00 h 0025 h mmu data register 1 mmu1 r/w 00 h 0026 h mmu data register 2 mmu2 r/w 00 h 0027 h mmu data register 3 mmu3 r/w 00 h 0028 h mmu data register 4 mmu4 r/w 00 h 0029 h reseved - - 002a h reseved - - 002b h uart transmit data register urtt w ff h 002c h uart receive data register urtr r 00 h 002d h uart status register urts r 0 * 000010 002e h uart control register urtc r/w 00 h 002f h reseved - - 0030 h control/status register lcc r/w 00 h 0031 h display h-timing register lch r/w ** 000000 0032 h display v-timing register lcv r/w * 1 0 * 000000 0033 h reserved - - 0034 h controler register dmc r/w 0 * 000000 0035 h source x-coordinate register dmx-1 r/w 00 h 0036 h source y-coordinate register dmy-1 r/w 00 h 0037 h x-width register dmdx r/w 00 h 0038 h y-width register dmdy r/w 00 h 0039 h destination x-coordinate register dmx2 r/w 00 h 003a h destination y-coordinate register dmy2 r/w 00 h 003b h pallet register dmpl r/w 00 h 003c h rom bank register dmbr r/w * 0000000 003d h vram page register dmvp r/w ****** 00 003e h reserved - - 003f h reserved - - notes : ? r/w indicates that there is at least one bit in the register is capable of read/write. (the register indicated by r/w includes the bit of special-purpose register for read). r indicates that the register is only fo r read. ? * indicates that the corresponding bit is undefined. * 1 the most significant bit is read only.
SM8521 - 22 - fig. 9-3 SM8521 memory map (3) address register name r/w initial 0040 h sg control register sgc r/w 0 *** 0000 0041 h rserved - - 0042 h sg0 output level control register sg0l r/w *** 00000 0043 h rserved - - 0044 h sg1 output level control register sg1l r/w *** 00000 0045 h rserved - - 0046 h sg0 time constant register (high) sg0th r/w **** 0000 0047 h sg0 time constant register (low) sg0tl r/w 00 h 0048 h sg1 time constant register (high) sg1th r/w **** 0000 0049 h sg1 time constant register (low) sg1tl r/w 00 h 004a h sg2 output level control register sg2l r/w *** 00000 004b h rserved - - 004c h sg2 time constant register (high) sg2th r/w **** 0000 004d h sg2 time constant register (low) sg2tl r/w 00 h 004e h sg-d/a direct output register sgda w 00 h 004f h rserved - - 0050 h timer control register 0 tm0c r/w **** 0000 0051 h timer data register 0 tm0d r/w 00 h 0052 h timer control register 1 tm1c r/w 0 *** 0000 0053 h timer data register 1 tm1d r/w 00 h 0054 h clock timer clkt * 1 00 h 0055 h reserved - - 0056 h reserved - - 0057 h reserved - - 0058 h reserved - - 0059 h reserved - - 005a h reserved - - 005b h reserved - - 005c h reserved - - 005d h reserved - - 005e h watchdog timer register wdt r 00 h 005f h watchdog timer control register wdtc r/w 38 h address register name r/w initial 0060 h sg0 waveform register 0 sg0w0 r/w undefined 0061 h sg0 waveform register 1 sg0w1 r/w undefined 0062 h sg0 waveform register 2 sg0w2 r/w undefined 0063 h sg0 waveform register 3 sg0w3 r/w undefined 0064 h sg0 waveform register 4 sg0w4 r/w undefined 0065 h sg0 waveform register 5 sg0w5 r/w undefined 0066 h sg0 waveform register 6 sg0w6 r/w undefined 0067 h sg0 waveform register 7 sg0w7 r/w undefined 0068 h sg0 waveform register 8 sg0w8 r/w undefined 0069 h sg0 waveform register 9 sg0w9 r/w undefined 006a h sg0 waveform register 10 sg0w10 r/w undefined 006b h sg0 waveform register 11 sg0w11 r/w undefined 006c h sg0 waveform register 12 sg0w12 r/w undefined 006d h sg0 waveform register 13 sg0w13 r/w undefined 006e h sg0 waveform register 14 sg0w14 r/w undefined 006f h sg0 waveform register 15 sg0w15 r/w undefined 0070 h sg1 waveform register 0 sg1w0 r/w undefined 0071 h sg1 waveform register 1 sg1w1 r/w undefined 0072 h sg1 waveform register 2 sg1w2 r/w undefined 0073 h sg1 waveform register 3 sg1w3 r/w undefined 0074 h sg1 waveform register 4 sg1w4 r/w undefined 0075 h sg1 waveform register 5 sg1w5 r/w undefined 0076 h sg1 waveform register 6 sg1w6 r/w undefined 0077 h sg1 waveform register 7 sg1w7 r/w undefined 0078 h sg1 waveform register 8 sg1w8 r/w undefined 0079 h sg1 waveform register 9 sg1w9 r/w undefined 007a h sg1 waveform register 10 sg1w10 r/w undefined 007b h sg1 waveform register 11 sg1w11 r/w undefined 007c h sg1 waveform register 12 sg1w12 r/w undefined 007d h sg1 waveform register 13 sg1w13 r/w undefined 007e h sg1 waveform register 14 sg1w14 r/w undefined 007f h sg1 waveform register 15 sg1w15 r/w undefined notes : ? r/w indicates that there is at least one bit in the register which is capable of read/write. (the register indicated by r/w includes the bit of special-purpose register for read). r indicates that the register is only fo r read. ? * indicates that the corresponding bit is undefined. * 1 bits 0 to 5 are read only. bits 6 and 7 are read/write.
SM8521 - 23 - hardware reset the hardware reset is an initial function for SM8521 system and comes from the following sources. external reset if the resetb pin is applied to low level in SM8521 operating, the hardware resets. watchdog timer overflow while watchdog timer overflows, the hardware resets. the above 2 hardware reset sources initializate the system. operating explanations hardware reset operation when the SM8521 is operating, a built-in pull-up resistor keeps the resetb pin at high level. if external circuit (like as reset ic etc.) applies low level voltage to resetb pin, the SM8521 is reset by hardware after approximately two instruction cycles. to ensure hardware reset execution keeps the resetb pin at low level over two instruction cycles of system clock. the pin back to high level from low level starts the warming up counter built-in SM8521. when the counter overflows, about 2 18 x main-clock leaves its hardware reset state and begins the program execution from the instruction at address 1020 h . in the warming up interval, SM8521 is in halt mode state. same as watchdog timer overflow case, the cpu leaves the hardware reset behind warming up period. interrupt function the SM8521 supports 10 interrupt sources. in these interrupts, watchdog timer and illegal instruction trap interrupts belong to non-maskable interrupts, the others, however, are maskable interrupts. 10 interrupt sources are shared to independent interrupt vector respectively, in the rom address area between 1000 h -101f h . and, the maskable interrupts are set 8 steps with priority level. with priority 8 levels with priority 1 level wdt (nmi) priority selector i 0 im 0 1 2 ps0 ps1 illegal instruction trap interrupt signal maskable interrupt interrupt process interrupt mask processor ie0 interrupt request latch ie1 ir0 ir1 interrupt request register interrupt enable register fig. 10 interrupt block diagram
SM8521 table 3 SM8521 interrupt vectors location and their priority vector location interrupt source symbol priority * 1000 h dma dmaint 1 1002 h timer 0 tim0int 2 1006 h external interrupt extint 3 1008 h uart transmit/receive complete uartint 4 100e h lcd controller lcdcint 5 1012 h timer 1 tim1int 6 1016 h clock ckint 7 101a h input/output port pioint 8 101c h watchdog timer overflow wdtint 101e h nmi, illegal instruction nmiint, illint * t he priority levels determine the order in which the chip process simultaneous interrupts. it also denotes the priority level of mask interrupts by setting the bits im2-im0 (bits 2-0 : ps0). register explanations ps0 (interrupt maskbit (im) of processor status 0) the bits im2-im0 can set the acceptable level for interrupt. the maskable interrupt requested by cpu is set 1 to 8 priority levels. these bits im2-im0 determine processing interrupts which priority levels. bits 2 to 0 : interrupt mask bits (im2-im0) bit content 000 all maskable interrupts recognized. 001 all maskable interrupts recognized. 010 maskable interrupts with 1 to 7 level recognized. 011 maskable interrupts with 1 to 6 level recognized. 100 maskable interrupts with 1 to 5 level recognized. 101 maskable interrupts with 1 to 4 level recognized. 110 maskable interrupts with 1 to 3 level recognized. 111 maskable interrupts with 1 to 2 level recognized. note : when an interrupt enables by interrupt mask bit, if all interrupt conditions are setup, then the cpu starts to the interrupt processing. - 24 -
SM8521 - 25 - ps1 (interrupt enable bit (i) of processor status 1) the bit i (bit 0 : ps1) enables/disables all maskable interrupts. after hardware reset, the bit i is set ? and so all maskable interrupts are in disable state. bit 0 : interrupt enable (i) except that write to processor status ps1 directly, the bit i can be set/cleared by the following special- purpose instructions. (under normal case, the special-purpose instructions are used.) di instruction : bit i is set ?? ei instruction : bit i is set ?? ie0 (interrupt enable register 0) the interrupt enable register ie0 is an 8-bit readable/writable register containing the settings for enable/disable to accept interrupt sources. bit 7 0 bit 7 : dma interrupt enable bit bit 6 : timer 0 interrupt enable bit bit 5 : sets ?? bit 4 : external interrupt enable bit bit 3 : uart interrupt enable bit bits 2 to 1 : set ?? bit 0 : lcd cotroller interrupt enable bit ie1 (interrupt enable register 1) the interrupt enable register ie1 is an 8-bit readable/writable register containing the settings for enable/disable to accept interrupt sources. bit 7 0 bit 7 : sets ?? bit 6 : timer 1 interrupt enable bit bit 5 : sets ?? bit 4 : clock interrupt enable bit bit 3 : sets ?? bit 2 : pio interrupt enable bit bits 1 to 0 : set ?? the interrupt enable register ie0 and ie1 are also used to wake up the chip from standby mode (stop mode, halt mode) by setting the interrupt to enable. if the interrupt enabled by the interrupt enable register ie0 and ie1 occurs, the chip will wake up from standby mode. but also there are interrupt sources which cannot use to wake up from stop mode. for more details, refer to "stand by function". dma tim0 - extint uart -- lcdc - tim1 - clk - pio - - bit content 0 disable 1 enable bit content 0 disable 1 enable bit content 0 disables to accept all maskable interrupts 1 enables to accept maskable interrupt. for each maskable interrupt can be enabled/ disabled by interrupt enable register ie0, ie1 and bits im2-im0.
SM8521 ir0 (interrupt request register 0) the interrupt request register ir0 is an 8-bit readable/writable register containing the setting for enable/disable to accept interrupt sources. bit 7 0 bit 7 : dma interrupt request bit bit 6 : timer 0 interrupt request bit bit 5 : sets ?? bit 4 : external interrupt request bit bit 3 : uart interrupt request bit bit 2 : sets ?? bit 1 : sets ?? bit 0 : lcd controller interrupt request bit ir1 (interrupt request register 1) the interrupt request register ir1 is an 8-bit readable/writable register containing the setting for enable/disable to accept interrupt sources. bit 7 0 bit 7 : sets ?? bit 6 : timer 1 interrupt request bit bit 5 : sets ?? bit 4 : clock interrupt request bit bit 3 : sets ?? bit 2 : pio interrupt request bit bit 1 to 0 : set ?? the interrupt request register ir0 and ir1 are also used to wake up the chip from standby mode (stop mode, halt mode) by setting the interrupt to enable. if the interrupt enabled by the interrupt request register ir0 and ir1 occurs, the chip will wake up from standby mode. but also there are interrupt sources which cannot use to wake up from stop mode. for more details, refer to "standby function". bit content 0 disable 1 enable dma tim0 - ext uart -- lcdc - tim1 - clk - pio - - bit content 0 disable 1 enable - 26 -
SM8521 - 27 - standby function the standby function is a function which temporarily stops program execution so as to conserve power. the standby mode is when the chip enters temporary stop state from the operating state, executing program. it contains both stop and halt modes, either of which can be selected according to your desires. if the cpu executes the stop mode or halt mode, the chip will switch to standby mode from an operating mode. if the wake up source of the standby mode encounters an interrupt the chip returns to operating mode from the standby mode. fig. 11 shows its state transition diagram. external reset request warming up end halt instruction execution halt mode wake up source stop instruction execution hardware reset normal operation operating mode halt mode stop mode standby mode stop mode wake up source internal/external reset request note : when the chip wakes up from stop mode, it returns to operating mode behind warming up period. fig. 11 state transition diagram note : the stop instruction is also used for clock change function, which its operation is different from switching the chip to stop mode, take care to use it.
SM8521 about hou to use halt mode and stop mode the chip switches back to the operating mode from the halt mode immediately after the wake up sources are encountered. for this reason, the halt mode is more suitable for systems that need to be immediately woke up frequently. and, all interrupt sources (other than illegal instruction trap) can wake up the chip from the halt mode. switching back to the operating mode from the stop mode after the wake up sources are encountered must pass a warming up period. in addition, the function blocks used by the main-clock cannot be used in the wake up from stop mode. since the sampling circuit is stopped, it can not accept the pint 0 input, either. for this reason, the stop mode (conserving more power than the halt mode) is suitable for systems that can easily support the longer time that it will take to get, back to the operating mode (warming up period) . in standby mode, i/o ports setting and output level for output ports are remained. before switches to standby mode, in order to reduce to the current through every pins, set with program. table 4 system state at standby mode halt mode stop mode transition method halt instruction execution stop instruction execution wake up method hardware reset, interrupt hardware reset, interrupt * 1 function blocks stop stop operating stop operating operating remain * 2 remain * 2 remain (interruptable) remain (interruptable) operating the timer used main-clock as counter clock is stop. it used external clock as counter clock can still operate. operating stop operating stop operating stop operating stop cpu main-clock sub-clock ram, register i/o port timer capture trigger uart lcdc waveform generator * 1 the interrupts used to wake up the chip from stop mode only have the external interrupts and the internal interrupts generated by operatable timer, and sio. * 2 general registers, control registers, and the other memory content all are remained. but something will be changed for the operatable blocks at stop mode (for example, interrupt flag register ir0, ir1 content, etc.) - 28 -
SM8521 - 29 - p0 to p3 (pio data register) bit 7 0 (x = 0, 1, 2, 3) note : in case of reading p0-p3 register on condition that control register is input state, data of those pins is read. in case of on condition that control register is output state, data of register is read. p0c to p2c (pio control register) bit 7 0 (x = 0, 1, 2) bits 7 to 6 : bits 5 to 4 : bits 3 to 2 : bits 1 to 0 : i/o ports the SM8521 supports four 8-bit i/o ports. each port can be selected one out of input, outpit, input with built-in pull-up resistor and open-drain in each 2-bit. internal bus input/output pins data register i/o control circuit control register fig. 12 pio block diagram p x 7p x 6p x 5p x 4p x 3p x 2p x 1p x 0 p x c7 p x c6 p x c5 p x c4 p x c3 p x c2 p x c1 p x c0 bit content 00 input 01 10 11 input (with pull-up resistor) output output (open-drain) bit content 00 input 01 10 11 input (with pull-up resistor) output output (open-drain) bit content 00 input 01 10 11 input (with pull-up resistor) output output (open-drain) bit content 00 input 01 10 11 input (with pull-up resistor) output output (open-drain)
SM8521 p3c (control register) bit 7 0 bits 7 to 6 : bits 5 to 4 : bits 3 to 2 : bits 1 to 0 : timer/counters the SM8521 supports 8-bit timer x 2, and clock timer x 1. one out of 8-bit prescaler output can be selected as an 8-bit timer input. p3c7 p3c6 p3c5 p3c4 p3c3 p3c2 p3c1 p3c0 bit content 00 input 01 10 11 input (with pull-up resistor) output/(timer 1 clock outputs through p3 7 ) output/(timer 1 clock outputs through p3 7 ) bit content 00 input 01 10 11 input (with pull-up resistor) output output (open-drain) bit content 00 input 01 10 11 input (with pull-up resistor) output output (open-drain) bit content 00 input 01 10 11 input (with pull-up resistor) output output (open-drain) - 30 - internal bus data register interrupt 8-bit prescaler 8-bit up-counter control register f ck comparator fig. 13 8-bit timer block diagram
SM8521 - 31 - 8-bit timer register tm0c, tm1c (control registers) bit 7 0 (x = 0, 1) bit 7 : start/stop bits 6 to 3 : set ? bits 2 to 0 : tm0d, tm1d (data register) bit 7 0 (x = 0, 1) bits 7 to 0 : content of counter (read), time con- stant (write) notes : after reset, the status of both tm0c and tm1c becomes 0 **** 000b, and both tm0d and tm1d becomes 00000000b. every time between the value of 8-bit up counter and the value of time constant register coincide in timer execution, output signal inverts. clock timer clock timer is for real time clock. dividing sub-clock (32.768 khz), 1 s or 1 min interrupt occurs. tm x c7 tm x c6 tm x c5 tm x c4 tm x c3 tm x c2 tm x c1 tm x c0 tm x d7 tm x d6 tm x d5 tm x d4 tm x d3 tm x d2 tm x d1 tm x d0 prescaler input clock for 8-bit up-counter 000 f ck /2 001 010 011 100 101 110 111 f ck /1 024 f ck /2 048 f ck /4 096 f ck /8 192 f ck /16 384 f ck /32 768 f ck /65 536 32.768 khz interrupt prescaler 1/60 counter data bus note : in case of run/reset bit is zero, both upper 8 bits in prescaler and all bits in 1/60 counter are reset. control register selector 1 s 1 min fig. 14 clock timer block diagram
SM8521 - 32 - clock timer register clkt (clock timer register) bit 7 0 bit 7 : run/reset bit 6 : minute/second bits 5 to 0 : value of counter (read only) watchdog timer register (wdt) prs2 (prescaler 2) prescaler prs2 generates the count clock to watchdog timer counter wdt. the following conditions are to clear all bits of prescaler prs2. when hardware reset. when watchdog timer counter wdt stopped. when counter wdt is cleared by writing ??to the bit wdtcr (bit 3 : wdtc). prescaler prs2 divides the frequency derived from input clock fc 10 (204.8 s : main-clock = 10 mhz), then fc 11 -fc 15 are output. wdt (watchdog timer counter register) watchdog timer counter wdt is an 8-bit read only register which counts up from input clock. wdtc (watchdog timer control register) watchdog timer control wdtc is an 8-bit read only register which sets watchdog timer to start/stop, counter clear designation, and selects the count clock. bit 7 0 bit 7 : watchdog timer start/stop bit (wdtst) bit 6 : operation select while watchdog timer overflow (wdtrn) bits 5 to 4 : set ?? bit 3 : counter clear bit (wdtcr) [write only bit] bits 2 to 0 : watchdog timer counter clock selection bits (wcnt2-wcnt0) bit count clock 000 fc 12 (819 s * 1 ) 001 fc 13 (1.639 ms * 1 ) 010 fc 14 (3.278 ms * 1 ) 011 fc 15 (6.578 ms * 1 ) 100 fx 5 (0.976 ms * 2 ) 101 fx 6 (1.95 ms * 2 ) 110 fx 7 (3.90 ms * 2 ) 111 fx 8 (7.81 ms * 2 ) wdtst wdtrn -- wdtcr wcnt2 wcnt1 wcnt0 1/2 1/2 1/2 1/2 1/2 fc 11 fc 12 fc 13 fc 14 fc 15 prs2 fc 2 bit content 0 timer stop [wdt is cleared.] 1 timer start bit content 0 hardware reset 1 non-maskable interrupt bit content 0 no clear 1 only in writing operation, wdt is cleared. bit status 0 1 second 1 1 minute bit status 0 counter reset 1 run * 1 the value in ( ) is the period when main-clock is 10 mhz. * 2 the value in ( ) is the period when sub-clock is 32.768 khz.
SM8521 - 33 - lcdc/dma the SM8521 supports lcd controller (lcdc) to control lcd pannel, in a kind of dot matrix, which is required external lcd drivers. lcdc transfers display data in the external vram to the lcd driver. the SM8521 supports a dma, which can transfer the data at the high speed, between rom and vram, vram and vram, and external ram and vram, without through the cpu. dma transfers display data in the rom and external ram to vram. source/destination register rom address generator vram address generator internal bus vram timing generator data composition circuit shift register external address bus interrupt (cpu) lcd driver external data bus fig. 15 lcd/dma block diagram
SM8521 - 34 - vram configulation vram configulation is shown below. vram, maximum 16 k bytes (160 x 200-dot x 2- phase or 200 x 160-dot x 2-plane), can be accessed. lcd diaplays a phase specified. address of vram0 and vram1 is a000 h -bfff h and c000 h -dfff h respectively. dma transfers rectangle display data, in arbitrary size specified in rom and external ram, to vram. note : do not write data directly to vram while transferring data to lcd driver (msb of lcc register is 1 and v-blank flag is 0). fig. 16 vram configuration dot 3 dot 2 dot 1 dot 0 0 1 0123 2 3 4 5 6 bit 7 4-dot/byte 160/200-dot vram 160-dot 200-dot 2-plane = 16 k-byte 160/200-dot dot data = 00 color 0 01 color 1 10 color 2 11 color 3
SM8521 - 35 - 160/200-dot 160/200-dot vram y2 x2 256-dot 256-dot rom y1 dy dx x1 dma transfer rom to vram transfer mode also, transfers between vrams. vram to vram transfer mode 160/200-dot 160/200-dot vram y2 x2 y1 x1 dy dx
SM8521 - 36 - vram rom + vram rom dot data = 0 : transparent vram dot data rom and vram rom dot data compound and overwrite mode to transfer display data, dma provides two modes. one is compound mode that source dot data zero is not stored into the destination. second is overwrite mode that any dot data is stored into the destination. fig. 17 an example of transfer rom to vram in compound mode
SM8521 - 37 - registers lcdc/dma registers are shown below. lcdc register is initialized at the system initialization. after setting each parameter, set the dma start bit to ? and execute halt instruction, then dma transfer starts. lcc (lcd control/status register) bit 7 0 bit 7 : display on/off bit 6 : display page a/b bit bits 5 to 4 : gradation control bits (depth of black and white on real lcd) note : gray scale white gray3 gray2 gray1 black bits 3 to 1 : lcdc/dma clock bits bit 0 : normal white bar bit lch (display horizontal timing register) bit 7 0 bits 7 to 6 : set ?? bit 5 : h-dot size bit bits 4 to 0 : h-timing bits note : v-blank width bit must not be filled with 0000b. otherwise, lcdc interrupt can not be effective. horizontal display cycle = ( shift clock x lcdc/dma clock ) x (h-timing + 1) shift clock = 40 (at h-dot size = 160), 50 (at h-dot size = 200) frame cycle = horizontal display cycle x (v-line size + v-blank width) gray 3 23 gray 2 white 2 3 black black black gray 1 gray 2 gray 1 0 0 0 1 1 1 dison dispg grad1 grad0 lccl2 lccl1 lccl0 norwh -- hd0t htim4 htim3 htim2 htim1 htim0 bit horizontal dot size 0 160 1 200 bit status 0 nor mal white 1 nor mal black bit lcdc/dma clock 000 f ck /2 001 010 011 100 101 110 111 f ck /4 f ck /6 f ck /8 f ck /10 f ck /12 f ck /14 f ck /16 bit display page 0 page a 1 page b bit display on/off 0 display off 1 display on bit 00 gray 3 white white 01 10 11 23 gradation choosen reserved
SM8521 - 38 - lcv (display vertical timing register) bit 7 0 bit 7 : v-blank bit (read only) bit 6 : sets ?? bits 5 to 4 : v-line size bits bits 4 to 0 : v-blank width bits note : v-blank width bit must not be filled with 0000b. otherwise, lcdc interrupt can not be effective. horizontal display cycle = (shift clock x lcdc/dma clock ) x (h-timing + 1) shift clock = 40 (at h-dot size = 160), 50 (at h-dot size = 200) frame cycle = horizontal display cycle x (v-line size + v-blank width) dmc (dma control register) bit 7 0 bit 7 : dma start bit bits 6 to 5 : set ?? bit 4 : increment y/decrement y bit (increment/decrement y-coordinate of source) bit 3 : increment x/decrement x bit (increment/decrement x-coordinate of source) bits 2 to 1 : transfer mode bits bit 0 : compound/over write bit bit source ? destination 00 vram ? vram 01 rom ? vram vblnk - vl1 vl0 vbwd3 vbwd2 vbwd1 vbwd0 bit status 0 non-vertical blank period 1 vertical blank period bit status 0 dma stops 1 dma starts transfering data bit status 0 increment y 1 decrement y bit status 0 increment x 1 decrement x 10 11 extend ram ? vram vram ? extend ram bit status 0 compound mode 1 overwrite mode bit vertical line size 00 100 01 10 160 200 dmst -- indcy indcx trn1 trn0 coovr
SM8521 - 39 - how to overturn a character in right and left. 4-dot data is transfered as a unit, from rom to vram or vram to vram. rom is composed of 8 bits. in case of "increment x" is effective, 8-bit data is transfered as shown below. bit 7 rom 0 vram dot3 dot2 dot1 dot0 bit 7 0 dot3 dot2 dot1 dot0 rom vram bit 7 0 dot3 dot2 dot1 dot0 bit 7 0 dot0 dot1 dot2 dot3 position of all specified dots, maximun 256, is overturned with right and left in horizontal. the heart of their x coordinates becomes an axis of symmetry. on the other hand, in case of "decrement x" is effective, 8-bit data is transferred as shown below. in each 4-dot data is automatically swapped in right and left. dmx17 dmx16 dmx15 dmx14 dmx13 dmx12 dmx11 dmx10 dmx1 (source x-coordinate register) dmy1 (source y-coordinate register) dmdx (x-width register (x-width-1)) dmdy (y-width register (y-width-1)) dmx2 (destination x-coordinate register) dmy2 (destination y-coordinate register) bit 7 0 bit 7 0 bit 7 0 bit 7 0 bit 7 0 bit 7 0 dmy27 dmy26 dmy25 dmy24 dmy23 dmy22 dmy21 dmy20 dmx27 dmx26 dmx25 dmx24 dmx23 dmx22 dmx21 dmx20 dmdy7 dmdy6 dmdy5 dmdy4 dmdy3 dmdy2 dmdy1 dmdy0 dmdx7 dmdx6 dmdx5 dmdx4 dmdx3 dmdx2 dmdx1 dmdx0 dmy17 dmy16 dmy15 dmy14 dmy13 dmy12 dmy11 dmy10
SM8521 - 40 - dmbr (rom bank register) dmbr register specifies rom's bank being transferred. (organization of bank is 256 x 256 dots. bank specifies external memory address irrespective of mmu.) bit 7 0 dmvp(dmvp register) dmvp register specifies a page (vram) in case of specifying vram to source and destination. bit 7 0 bits 7 to 2 : set ?? bit 1 : destination page a/b bit 0 : source page a/b dmpl (pallet register) dmpl register specifies gradation to dot data. when transferring, gradation data concerned with dot data of the dmpl register is stored to vram. bit 7 0 bits 7 to 6 : dot data color 0 bits 5 to 4 : dot data color 1 bits 3 to 2 : dot data color 2 bits 1 to 0 : dot data color 3 example : when dot data color 2 (10b) is specified under the status of the dmpl register filled with ** 01 **** b, bit 4 and 5 of the dmpl register are automatically selected. dot data changes from color 2 (10b) to color 1 (01b). then the dot data color 1 moves to specified vram. col31 col30 col21 col20 col11 col10 col01 col00 dmpl note : color 0-3 are not depth gradation. depth of black and white on lcd is fixed by gradiation control bit of the lcc registe r. rom/vram dot data = color 2 (10b) color 3 color 2 01 color 1 color 0 vram dot data = color 1 (01b) fig. 18 how to select gradations - dmbr6 dmbr5 dmbr4 dmbr3 dmbr2 dmbr1 dmbr0 ------ souab desab bit content 0 destination page a 1 destination page b bit content 0 source page a 1 source page b
SM8521 - 41 - sound generator the SM8521 supports two waveform generators concerning arbitrary waveform output channel and one noise generator channel. after each channel's signal is amplified through each variable register, a digital mixer mixes them into one and d/a outputs it. address generator scale counter internal bus internal bus waveform generator waveform generator waveform memory digital mixer d/a sound output d/a direct output channel noise sound generator (random rectangular waveform) sg1 sg0 sg2 fig. 19 sound generator block diagram waveform generator the data, 4-bit x 32 steps, stored in the waveform register (sgw0-15) is output at the timing of fck (main clock) divided by time constant register. digital mixer 4-bit data generated from each generator is expanded to sixteen times as large as original 4-bit data. those expanded data is added to one another after passing through digital attenuator (0, 1/32, 2/32, .... 31/32) of which attenuation rate is specified by output level control register. note : attention to the sum total of each sound generator, not exceeding capacity of digital mixer. noise sound register false noise, of which maximum frequency is based on cycle divided fck (main clock) by time constant register, is output. d/a direct output register (in digital mixer) when all sound generator 0, 1 and 2 are disable, the data stored in this register is directly effective as d/a input, provided that the data is stored in the sgda register and both sound output enable register and d/a direct output enable registers are set. note : all 12 bits of each sg0, sg1 and sg2 must not be filled with 0. if all 12 bits become 0, d/a can not perform correct output.
SM8521 - 42 - sound waveform register sound waveform generator can outputs 16-tone wedge and 32-step sign waveform as shown below. step 01234567891111111111222222222233 0123456789012345678901 note : a period of one step is variable based on the value of time constant register (sg0, sg1 and sg2 composed of 12 bits). the period can be lead from the formula shown below. period = f ck (n-1) period : time of one step f ck : system oscillation frequency n : value of time constant register
SM8521 - 43 - in order of low and high, each 4-bit data is specified. each sg0 and sg1 waveform register stores 4-bit x 32-step data as shown below. refer to sg0 and sg1 waveform registers in fig. 9-3. the most significant bit of each 4-bit data indicates positive and negative. that means, range of each 4-bit data is 8 to +7. note : waveform register read/write is possible only when sg is disable. 7 0 step0 step2 step4 step6 step8 step10 step12 step14 step1 step3 step5 step7 step9 step11 step13 step15 0 1 2 3 4 5 6 7 step16 step18 step20 step22 step24 step26 step28 step30 step17 step19 step21 step23 step25 step27 step29 step31 8 9 a b c d e f 3 4 fig. 20 sound waveform register +2.5 v +5.0 v d/a output level time rump-up period rump-down period fig. 21 example of d/a output notes : mute level of the d/a should be created by software. attenuate not to exceed capacity of d/a output level (0-5 v) by software. to avoid pop-noise, make rump-up and down period by software.
SM8521 - 44 - registers sgc (control register) bit 7 0 bits 7 : sound output enable bits 6 to 4 : set ?? bit 3 : d/a direct output enable bit 2 : sg2 output enable bit 1 : sg1 output enable bit 0 : sg0 output enable sg0l, sg1l (output level control register ; 0, 1/32, 2/32?1/32) bit 7 0 (x = 0, 1) the value of output level control register decides the digital attention rate. sg0tl, sg1tl (time constant register ; low) bit 7 0 (x = 0, 1) sg0th, sg1th (time constant register ; high) bit 7 0 (x = 0, 1) bits 7 to 4 : set ?? a period of one step is variable based on the value of time constant register (sg0tl, sg0th, sg1tl and sg1th composed of 12 bits.) sg0w0-15, sg1w0-15 (waveform register 0-15) bit 7 0 (x = 0, 1)(y = 0 to 15) bits 7 to 4 : waveform data low order bits 3 to 0 : waveform data high order sg2l (output level control register ; 0, 1/32, 2/32?1/32) bit 7 0 bits 7 to 5 : set ?? the value of output level control register decides the digital attenuation rate. sg2tl (time constant register ; low) bit 7 0 sg2th (time constant register ; high) bit 7 0 bits 7 to 4 : set ?? a period of one step is variable based on the value of time constant register (sg2tl and sg2th composed of 12 bits). sgda (d/a direct output register ; write only) bit 7 0 the value of sgda register directly transfers digital mixer. notes : time constant register must be written by "movw" instruction. each time constant register must not be filled with all "0" or only the low significant bit is "1". sondout --- dirout sg2out sg1out sg0out --- sg2l4 sg2l3 sg2l2 sg2l1 sg2l0 sg2tl7 sg2tl6 sg2tl5 sg2tl4 sg2tl3 sg2tl2 sg2tl1 sg2tl0 ---- sg2th3 sg2th2 sg2th1 sg2th0 sgda7 sgda6 sgda5 sgda4 sgda3 sgda2 sgda1 sgda0 --- sgxl4 sgxl3 sgxl2 sgxl1 sgxl0 sgxtl7 sgxtl6 sgxtl5 sgxtl4 sgxtl3 sgxtl2 sgxtl1 sgxtl0 ---- sgxth3 sgxth2 sgxth1 sgxth0 sgxwy7 sgxwy6 sgxwy5 sgxwy4 sgxwy3 sgxwy2 sgxwy1 sgxwy0
SM8521 - 45 - mmu the SM8521 supports an mmu used to external memory area expansion. memory area 1000 h -9fff h , can be expanded to 2m-byte in each 8k-byte unit. mmux is selected depends on cpu address. note : cpu can not access lower 4 k-byte of mmu0 because of occupied by internal ram and register file. on the other hand, each 8 k-byte of external rom is accessible as dma's address. 7 15 12 13 0 mmu0 (0000 h -1fff h ) cpu address mmu1 (2000 h -3fff h ) mmu2 (4000 h -5fff h ) mmu3 (6000 h -7fff h ) 0 20 12 13 external memory address 0 mmu4 (8000 h -9fff h ) fig. 22 an example of mmu switching flow and mapping
SM8521 notes : at reset, mmu0 is disable and internal rom is enable. (1000 h -1fff h ). at setting data into mmu0 once, internal rom becomes disable and mmu0 becomes enable. in case of changing to external rom mode by putting some data into mmu register, use immediate r in "mov" instruction (mov r, r or mov r, r). data in the next internal rom address will be fetched at the same time of executing the instruction. only one byte instruction can be followed when setting data to mmu0 register. a000 h 6000 h 8000 h 4000 h 1000 h 2000 h 0400 h 0000 h internal i/o / ram 1fffff h rom/flash vram e000 h ffff h extend i/o extend ram external rom/flash 000000 h 4 k-byte 8 k-byte 8 k-byte 8 k-byte 8 k-byte external rom/flash external rom/flash external rom/flash * notes a000 h 6000 h 8000 h 4000 h 1000 h 2000 h 0400 h 0000 h internal i/o / ram vram e000 h ffff h extend i/o extend ram external rom/flash 4 k-byte 8 k-byte 8 k-byte 8 k-byte a000 h 6000 h 8000 h 4000 h 1000 h 2000 h 0400 h 0000 h internal i/o / ram vram e000 h ffff h extend i/o extend ram external rom/flash 8 k-byte 8 k-byte 8 k-byte 8 k-byte in case of mmu0 is disable (at reset) in case of mmu0 is enable external rom/flash external rom/flash external rom/flash external rom/flash external rom/flash internal rom 8 k-byte external rom/flash 4 k-byte external rom/flash fig. 23 mmu mapping fig. 24 comparison figure mmu 0 between disable and enable - 46 -
SM8521 - 47 - universal asynchronous receiver and transmitter (uart) interface SM8521 supports 1-channel universal asynchronous receiver and transmitter interface (uart) . the uart interrupt has the following features. transmitter and receiver are independent each other, full duplex communication possible. ?receiver is consisted of duplex buffer, able to receive data continuously. ?the dedicated register for baud rate generator is built-in. it is possible to choose transfer format as following. ?stop bit : 1-bit/2-bit ?parity bit : even parity/odd parity/no parity ? receive error can be detected. ?frame error ?parity error ?overrun error note : uart baud rate is fixed at [timer 0 output/32]. regarding timer 0, refer to "8-bit timer register tm0c". data bus receiver data register urtr transmit data transmit control register urtt control register urtc : a control register mapped by register file receive data receive control shift register p status register urts interrupt request signal to bit ir03 (bit 3 : ir0) p divider timer 0 output (divided by 16) t x d p7 0 /r x d fig. 25 uart block diagram
SM8521 uart transmit data register (urtt) transmit data register urtt is an 8-bit write only register which stores the uart transmit data. when the transmission operation starts, the content of this register lsb first is output from p7 1 /txd pin. uart receive data register (urtr) receive data register urtr is an 8-bit read only register which stores the uart receive data. when the receive operation starts, the receive data lsb first will be moved into the receive data shift register from p7 0 /rxd pin. once the receive operation is complete, the content of the receive data shift register is loaded into this receive data register urtr (duplex buffer). uart status register (urts) status register (urts) is an 8-bit read only register containing the flags of the uart interface transmit/ receive status. bit 7 0 bits 7 to 6 : set ? bit 5 : receiver busy bit (rbsy) bit 4 : overrun error bit (or) bit 3 : frame error bit (fe) bit 2 : parity error bit (pe) bit 1 : transmit data register empty bit (tdre) bit 0 : receiver data register full bit (rdrf) - - rbsy or fe pe tdre tdrf bit content 0 uart receiver is other than the following. 1 uart receiver processing incoming data. bit content 0 clear condition (1) while reading the status register urts (2) hardware reset 1 set condition (1) while overrun error occurs (the next receive is complete under the bit rdrf = 1 . ) at receive data bit content 0 clear condition (1) while reading the status register urts (2) hardware reset 1 set condition (1) while frame error occurs (stop bit = 0 is detected.) at receive data. bit content 0 clear condition (1) while reading the status register urts (2) hardware reset 1 set condition (1) parity error occurs at receive data bit content 0 clear condition (1) while writing to transmit data register urtt 1 set condition (1) while having finished transmitting operation. (2) hardware reset bit content 0 clear condition (1) while reading from receive data register urtr (2) hardware reset 1 set condition (1) while receive data is transferring to receive data register urtr from receive data shift register. - 48 -
SM8521 - 49 - uart control register (urtc) control register urtc is an 8-bit readable/writable register specifying transfer format setting and transmit/receive operation controlling. bit 7 0 bits 7 to 5 : set ?? bit 4 : transmit enable bit (te) setting the bit te to ?? starts the built-in baud rate generator and the interface enters transmissible status. in such status, if a transmit data is written to the transmit data register urtt, then will start the transmission operation. if the bit te clears to ?? the transmitter will be initializated. bit 3 : receive enable bit (re) setting the bit re to ?? starts the built-in baud rate generator and the interface enters receivable status. in such status, if the start bit (= ?? is detected, then will start the receive operation. if the bit re clears to ?? the receiver will be initializated. bit 2 : parity enable bit (pen) bit 1 : even/odd parity bit (eop) bit 0 : stop bit length bit (sbl) - - - te re pen eop sbl bit content 0 transmitter disable 1 transmitter enable (built-in baud rate generator operates) bit content 0 receiver disable 1 receiver enbable (built-in baud rate generator operates) bit content 0 transmit : the data with parity bit receive : parity enable 1 transmit : the data without parity bit receive : parity disable bit content 0 even parity 1 odd parity bit content 0 stop bit : 1 bit 1 stop bit : 2 bits
SM8521 transfer format according to setting stop bit and parity bit by control register urtc, transfer format indicated by fig. 26 can be selected. urtc pen sbl (bit 2) (bit 0) 00 01 10 11 st st st st bit 0 bit 0 bit 0 bit 0 bit 1 bit 1 bit 1 bit 1 bit 2 bit 2 bit 2 bit 2 bit 3 bit 3 bit 3 bit 3 bit 4 bit 4 bit 4 bit 4 bit 5 bit 5 bit 5 bit 5 bit 6 bit 6 bit 6 bit 6 bit 7 bit 7 bit 7 bit 7 p p stp stp stp stp stp stp transfer format (transfer direction) st : start bit, p : parity bit, stp : stop bit fig. 26 transfer format fig. 27 8-bit mode transfer format (example for parity added and 2 stop bits) st bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity stp stp - 50 -
SM8521 - 51 - instruction set the instruction set of the sm85cpu has the following characteristics : the instruction set is the result of subtle design and consists of 67 types of basic instructions. the powerful bit manipulation instructions includes plural bits transfer, logical operation between bits, and the bit test and jump instructions that incorporates a test and condition branch in the same instruction. ?there are transfer, operation and conditional branch instructions for 16-bit. the actions of transfer, operation and long jump for word data can be processed in high speed. there are arithmetic instructions for multi- plication and division. multiplication : 8-bit x 8-bit ? 16-bit division : 16-bit x 16-bit ? 16-bit remaining 8-bit ?23 types of memory addressing mode ?by variety of memory addressing modes, the accessing to ram, rom, and register file can be operated . definition of symbols instruction summary load instructions instruction operand function clr dst dst ? 0 (clear) mov dst, src dst ? src (move) movm dst, im, src dst ? (dst and im) or src (move under mask) movw dst, src dst ? src (move word) pop dst dst ? @sp, sp ? sp+1 (pop from stack) popw dst dst ? @sp, sp ? sp+2 (pop word from stack) push src sp ? sp?, @sp ? src (push to stack) pushw src sp ? sp?, @sp ? src (push word to stack) symbol explanation pc program counter sp stack pointer @sp indirect stack pointer ps0 processor status 0 ps1 processor status 1 c carry flag z zero flag s sign flag v overflow flag d decimal complement flag h half carry flag bf bit flag i interrupt enable dst destination src source cc condition code
SM8521 arithmetic operation instructions logical operation instructions program control instructions instruction operand function adc dst, src dst ? dst+src+c (add with carry) adcw dst, src dst ? dst+src+c (add word with carry) add dst, src dst ? dst+src (add) addw dst, src dst ? dst+src (add word) cmp dst, src dst src (compare) cmpw dst, src dst?rc (compare word) da dst dst ? da dst (decimal adjust) dec dst dst ? dst 1 (decrement) inc dst dst ? dst+1 (increment) div dst, src dst ? dst/src, src ? dst mod src (divide) decw dst dst ? dst 1 (decrement word) exts dst extend sign (extend sign) sbc dst, src dst ? dst src c (subtract with carry) mult dst, src dst ? dst x src (multiply) sub dst, src dst ? dst src (subtract) incw dst dst ? dst+1 (increment word) neg dst dst ? dst (negate) sbcw dst, src dst ? dst src c (subtract word with carry) subw dst, src dst ? dst src (subtract word) instruction operand function and dst, src dst ? dst and src (logical and) andw dst, src dst ? dst and src (logical and word) com dst dst ? not dst (complement) or dst, src dst ? dst or src (logical or) orw dst, src dst ? dst or src (logical or word) xor dst, src dst ? dst xor src (logical exclusive or) xorw dst, src dst ? dst xor src (logical exclusive or word) instruction operand function bbc src, dst if src = 0 then pc ? pc+dst (branch on bit clear) bbs src, dst if src = 1 then pc ? pc+dst (branch on bit set) br cc, dst if cc = true then pc ? pc+dst (branch) call dst sp ? sp 2, @sp ? pc, pc ? dst (call subroutine) cals dst sp ? sp 2, @sp ? pc, pc ? dst (short call subroutine) dbnz r, dst r ? r 1, if r 0 then pc ? pc+dst (decrement and branch on non-zero) iret ps1 ? @sp, sp ? sp+1, pc ? @sp, sp ? sp+2 (return from interrupt) jmp cc, dst if cc = true , then pc ? dst (jump) ret pc ? @sp, sp ? sp+2 (logical exclusive or word) - 52 -
SM8521 - 53 - bit operation instructions rotate and shift instructions cpu control instructions instruction operand function band bf, src bf ? bf and src (bit and) bclr dst dst ? 0 (bit clear) bcmp bf, src bf src (bit compare) bmov dst, src dst ? src (bit move) bor dst, src dst ? bf or src (bit or) bset dst dst ? 1 (bit set) btst dst, src dst and src (bit test) bxor bf, src bf ? bf xor src (bit exclusive or) instruction operand function rlc dst (rotate left through carry) rr dst (rotate right) rrc dst (rotate right through carry) sll dst (shift left logical) sra dst (shift right arithmetic) srl dst (shift right logical) swap dst (swap nibbles) instruction operand function clrc c ? 0 (clear carry flag) comc c ? not c (complement carry flag) di i ? 0 (disable interrupt) ei i ? 1 (enable interrupt) halt move to halt mode (halt cpu) nop no opreration (no opreration) setc c ? 1 (set carry flag) stop go to stop mode (stop cpu)
SM8521 addressing mode there are 23 types of addressing mode to perform memory accessing in sm85cpu. the relationships between the addressing modes and the operand are shown in the following table 5. table 5 addressing mode summary name symbol range operand * 1 implied to specify the carry(c) and interrupt enable (i) in the instruction code. register r r = r0-r7 general register [byte] register pair rr r = rr0, rr2, ?, rr14 general register [word] register file r r = 0 to 255 (r0-r15) register file (0000 h -007f h ) and (0080 h -00ff h ) [byte] register file pair rr r = 0, 2, ?254 (rr0, rr2, ?, rr14) register file (0000 h -007f h ) and (0080 h -00ff h ) [byte] register indirect @r r = r0-r7 memory (0000 h -00ff h ) [byte] register indirect auto increment (r)+ r = r0-r7 memory (0000 h -00ff h ) [byte] register indirect auto decrement ?r) r = r0-r7 memory (0000 h -00ff h ) [byte] register index n(r) * 2 n = 00 h -ff h , r = r1-r7 memory (0000 h -00ff h ) [byte] register pair indirect @rr rr = rr0, rr2, ?, rr14 memory (0000 h -ffff h ) [word/byte] register pair indirect auto increment (rr)+ rr = rr0, rr2, ?, rr14 memory (0000 h -ffff h ) [word/byte] register pair indirect auto decrement ?rr) rr = rr0, rr2, ?, rr14 memory (0000 h -ffff h ) [word/byte] register pair index nn(rr) * 3 nn = 0000 h -ffff h rr = rr2, rr4, ?, rr14 memory (0000 h -ffff h ) [word/byte] index indirect @nn(r) * 2 nn = 0000 h -ffff h r = r1-r7 memory (0000 h -ffff h ) [word] immediate im im = 00 h -ff h the immediate data in the instruction code [byte] immediate long iml iml = 0000 h -ffff h the immediate data in the instruction code [word] bit b b = 0 to 7 register file (0000 h -007f h ) and memory (0080 h -00ff h , ff00 h -ffff h ) [bit] (1 bit of 1 byte pointed by r, n(r) and dap) port p register file (0010 h -0017 h ) [byte] relative ra pc ?128 to pc + 127 program memory (1000 h -ffff h ) direct da da = 0000 h -ffff h memory (0000 h -ffff h ) [byte] direct short das das = 1000 h -1fff h program memory (1000 h -1fff h ) direct special page dap dap = ff00 h -ffff h program memory (ff00 h -ffff h ) [byte] direct indirect @da da = 0000 h -ffff h memory (0000 h -ffff h ) * 1 the data indicated by [ ] is the unit of possible to use in load and arithmetic instructions. * 2 r0 can not be used. * 3 rr0 can not be used. - 54 -
SM8521 - 55 - system configuration example sram (8/16k-byte) common driver lh1527 lcd panel (200/160 x 100/160/200-dot) sm85cpu 5 v ram (1 k-byte) rom (4 k-byte) timer ?clock ?watchdog timer sound generator amp mrom flash sram 8-bit max. 2 m-byte sram max. 8 k-byte uart mmu pio pc ir key matrix/touch key lcdc/dma vlcd 5 v segment driver lh1528 vlcd 5 v ?electronic organizer
SM8521 - 56 - 1 38 102 0.5 0.20 65 64 39 103 128 package base plane 0.1 0.1 20.0 22.6 0.2 0.3 0.2 0.3 14.0 15.6 0.2 typ. 0.08 0.15 0.05 1.95 0.2 0.9 0.08 m 0.10 (1.3) (1.3) (1.3) (1.3) 16.6 128 qfp (qfp128-p-1420)

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